A continuing goal of integrated circuit fabrication is to decrease the amount of semiconductor real estate consumed by integrated circuit devices, and to thereby increase the level of integration.
Memory may utilize a large array of memory devices. Accordingly, reduction in the size of individual memory devices may translate into a large increase in the bit density. Common memory devices are dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and nonvolatile devices (so-called flash devices). The nonvolatile devices may be incorporated into NAND or NOR memory array architectures.
The size of a memory device may be expressed in terms of the smallest feature size utilized in fabrication of the memory device. Specifically, if the smallest feature size is designated as “F,” the memory device dimensions may be expressed in units of F2. Conventional DRAM memory frequently comprises dimensions of at least 6 F2, and SRAM may require even more semiconductor real estate.
A type of memory that potentially consumes very little semiconductor real estate is so-called cross-point memory. In cross-point memory, a memory cell occurs at overlap between a wordline and a bitline. Specifically, a material which undergoes a stable and detectable change upon exposure to current is provided between the wordline and bitline. The material may be, for example, a perovskite material, a chalcogenide material, an ionic transport material, a resistive switching material, a polymeric material and/or a phase change material. Since the memory cell may be confined to a region of overlap of a bitline and wordline, the memory cell may theoretically be formed to dimensions of 4 F2 or less.
Problems encountered in closely packing cross-point memory may include disturbance mechanisms (or so-called cross-talk) occurring when data transfer to or from one memory cell influences a neighboring memory cell.
It is desired to develop improved methods for forming highly integrated circuitry, and to develop improved highly integrated circuit constructions.